The present invention relates in general to a method of manufacture of a semiconductor device and to a semiconductor device, more particularly, the invention relates to a technique that is effective when applied to the manufacture of a semiconductor device having an MISFET (Metal Insulator Semiconductor Field Effect Transistor).
A method of forming a contact hole by using a self aligned contact process is conventionally known. A contact hole is formed, for example, in the following manner: A silicon nitride film and a silicon oxide film are formed successively over the main surface of a semiconductor substrate so as to cover a gate electrode with these films. Using a photoresist pattern that has been formed over the silicon oxide film by photolithography as an etching mask, the silicon oxide film is etched under conditions facilitating preferential etching of the silicon oxide film while using the silicon nitride film as an etching stopper film. The silicon nitride film is then etched using the photoresist pattern as an etching mask under conditions facilitating preferential etching of the silicon nitride film, whereby a contact hole from which a semiconductor substrate region is exposed is formed.
Japanese Unexamined Patent Publication No. 2003-273240 describes the manufacture of a semiconductor device having an n-type-FET and a p-type-FET, which comprises the steps of forming a first insulating film generating a tensile stress in the channel formation region of the n-type-FET, so as to cover gate electrodes of the n-type-FET and p-type-FET, while covering a semiconductor region between the gate electrode of the p-type-FET and an element isolation region of a semiconductor substrate; selectively removing the first insulating film over the p-type-FET by etching; forming a second insulating film generating a compression stress in the channel formation region of the p-type-FET over the n-type-FET and p-type-FET, so as to cover the gate electrodes thereof; and selectively removing the second insulating film over the n-type-FET
[Patent Document 1]
    Japanese Unexamined Patent Publication No. 2003-273240